One or more example embodiments of inventive concepts relate to a correlated double sampling (CDS) circuit such as a CDS circuit configured to decrease a settling time and an image sensor including the same.
A single-slope analog-digital converting method has been widely used as an analog-digital converting method in the field of image sensor.
In this method, a ramp signal and a pixel signal having a certain voltage are compared with each other and a time or a point of time at which a voltage of the ramp signal and a voltage of the pixel signal are equal to each other is converted into a digital signal on the basis of a result of comparing these signals with each other.
In a column parallel analog-digital converting method, one or more column analog-digital converters (ADCs) should be integrated in one pixel pitch. Thus, the single-slope analog-digital converting method has been widely used in consideration of layout area and power consumption.
An image sensor employs CDS, and counts a signal sampled through CDS, e.g., the difference between a reset signal and an image signal, and outputs a digital signal.
Recently, high-resolution and high-frame-rate (HFR) driving technologies have been used in the field of complementary metal-oxide semiconductor (CMOS) image sensor (CIS). In particular, when an image of a fast moving object is captured, performing an HFR operation of 120 fps (frame per second) or more is very important to suppress image distortion caused by a rolling shutter of a CIS.
For the HFR operation, a technique of decreasing a pixel settling time during an operation of an ADC of an image sensor has been suggested.